Power control algorithms (PCAs) and/or finite state machines (FSMs) on computing platforms vary by product line and system vendor. PCAs and FSMs can be divided into different blocks for different integrated circuits (ICs) and generally are not centralized.
Application specific standard product (ASSP) data initialization and boot strapping are done in a static fashion using passive components and complex programmable logic devices (CPLDs) without an integrated versatile design. Because application specific integrated circuits (ASIC) have a hardcoded design, a challenge is created to satisfy the dynamic requirements of system developers.
Attempts to improve in this area include field programmable gate arrays (FPGAs) in a package with ICs that include the ability to be reconfigured. These FPGAs lack the ability for boot strapping and power management
There is a need to improve the block unification, size and power reduction, boot strapping, and power management of a multi-purpose power controller and ASSP.